High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory.
In recent years, there has been an effort to reduce a chip size for semiconductor devices. As part of that effort to reduce the chip size, reduction of a logic circuit area through layout optimization has been playing an important role as well as area reduction through improved microfabrication processes.
Generally, a layout of the area for logic circuits includes one or more standard cells. A standard cell is a small-scale circuit unit including a group of at least one transistor and interconnect structures with a standardized constant width. The standard cell may provide a logic function or a storage function. Typically, the standard cell provides a substrate contact (sub-contact) for an n-channel transistor and a well-contact for a p-channel transistor within the standard cell in order to supply the transistor in the standard cell with a stable bulk voltage. Because standard cells arrangement allows various combinations of standard cell types next to each other in the area for logic circuits, standard cells are designed to provide the sub-contact and well-contact without fail regardless of adjacent standard cell type combinations.
A delay circuit includes a capacitance and a resistance on a signal line and provides a delay. Typically, a delay circuit that may be provided as a standard cell includes an inverter, a resistance element, and a capacitive element. The delay circuit occupies a relatively large area for at least two reasons. First, space tends to be created in an area adjacent to the resistance element or an area adjacent to the transistor due to a difference in area between the resistance element and the transistor. Second, the resistance element may be surrounded by any sub-contact or well-contact included in the standard cell. Thus, reducing the space as well as the number of sub-contacts and well-contacts adjacent to the resistance element may be desired for the area reduction of the delay circuit.